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ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue jul.25.2004 rev. 1.1 delete icc1/ i sb spec. sep.21.2004 rev. 1.2 a dding skinny p-dip a ug.18.2005 rev. 1.3 revised stsop package outline dimension mar.26.2008 rev. 1.4 rev. 1.5 revised v term to v t1 and v t2 revised test condition of i sb1 /i dr added ll spec. revised test condition of i cc revised features & ordering information lead free and green package available to green package available deleted t solder in absolute maximun ratings added packing type in ordering information feb.2.2009 apr.17.2009 rev. 1.6 rev. 1.7 revised package outline dimension in page 10 revised ordering information in page 11 revised package outline dimension in page 9 ma y .7.2010 aug.25.2010
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 8/10/12/15ns ? low power consumption: operating current : 110/100/90/80ma (typ.) standby current : 1ma (typ.) 2 a (typ.) ll-version ? single 5v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data retention voltage : 2.0v (min.) ? green package available ? package : 28-pin 300 mil soj 28-pin 300 mil skinny p-dip 28-pin 8mm x 13.4mm stsop general description the ly61256 is a 262,144-bit high speed cmos static random access memory organized as 32,768 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly61256 is well designed for high speed system application. easy expansion is provided by using an active low chip enable(ce#). the active low write enable(we#) controls both writing and reading of the memory. the ly61256 operates from a single power supply of 5v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, typ.) operating(icc,typ.) ly61256 0 ~ 70 4.5 ~ 5.5v 8/10/12/15ns 1ma 110/100/90/80ma ly61256(e) -20 ~ 80 4.5 ~ 5.5v 8/10/12/15ns 1ma 110/100/90/80ma ly61256(i) -40 ~ 85 4.5 ~ 5.5v 8/10/12/15ns 1ma 110/100/90/80ma ly61256(ll) 0 ~ 70 4.5 ~ 5.5v 8/10/12/15ns 2 a(ll) 110/100/90/80ma ly61256(lle) -20 ~ 80 4.5 ~ 5.5v 8/10/12/15ns 2 a(ll) 110/100/90/80ma ly61256(lli) -40 ~ 85 4.5 ~ 5.5v 8/10/12/15ns 2 a(ll) 110/100/90/80ma functional block diagram decoder i/o data circuit control circuit 32kx8 memory array column i/o a0-a14 vcc vss dq0-dq7 ce# we# oe# pin description symbol description a0 - a14 address inputs dq0 ? dq7 data inputs/outputs ce# chip enable input we# write enable input oe# output enable input v cc power supply v ss ground
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss a14 vcc a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 ly61256 skinny p-dip/soj 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a13 ce# oe# we# stsop i/o4 a11 a9 a8 a13 i/o3 a10 a14 a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 ly61256 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 oe# we# ce# absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 6.5 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a 0 to 70(c grade) -20 to 80(e grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode ce# oe# we# i/o operation supply current standby h x x high-z i sb1 output disable l h h high-z i cc read l l h d out i cc write l x l d in i cc note: h = v ih , l = v il , x = don't care.
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih *1 2.4 - v cc +0.5 v input low voltage v il *2 - 0.5 - 0.8 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh = -4m a 2.4 - - v output low voltage v ol i ol = 8m a - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il , i i/o = 0ma others at v il or v ih -8 - 110 190 m a -10 - 100 180 m a -12 - 90 160 m a -15 - 80 140 m a standby power supply current i sb1 ce# v R cc -0.2v, normal - 1 5 m a ce# v R cc -0.2v, others at 0.2v or v cc -0.2v ll - 2 50 a notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc -0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh / i ol = -4ma/8m a
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? ac electrical characteristics (1) read cycle parameter sym. ly61256-8 ly61256-10 ly61256-12 ly61256-15 unit min. max. min. max. min. max. min. max. read cycle time t rc 8 - 10 - 12 - 15 - ns a ddress access time t aa - 8 - 10 - 12 - 15 ns chip enable access time t ace - 8 - 10 - 12 - 15 ns output enable access time t oe -4-5-6 - 7ns chip enable to output in low-z t clz * 2-2-3- 4 -ns output enable to output in low-z t olz * 0-0-0- 0 -ns chip disable to output in high-z t chz *-4-5-6 - 7ns output disable to output in high-z t ohz *-4-5-6 - 7ns output hold from a ddress change t oh 3-3-3- 3 -ns (2) write cycle parameter sym. ly61256-8 ly61256-10 ly61256-12 ly61256-15 unit min. max. min. max. min. max. min. max. write cycle time t wc 8 - 10 - 12 - 15 - ns a ddress valid to end of write t aw 6.5 - 8 - 10 - 12 - ns chip enable to end of write t cw 6.5 - 8 - 10 - 12 - ns a ddress set-up time t as 0-0-0- 0 -ns write pulse width t wp 6.5-8-9- 10 -ns write recovery time t wr 0-0-0- 0 -ns data to write time overlap t dw 5-6-7- 8 -ns data hold from end of write time t dh 0-0-0- 0 -ns output active from end of write t ow * 1.5-2-3- 4 -ns write to output in high-z t whz *-5-6-7 - 8ns *these parameters are guaranteed by device characterization, but not production tested.
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout data valid t oh oe# t ace ce# t aa address t rc high-z high-z t clz t olz t oe t chz t ohz notes : 1.we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low . 3.address must be valid prior to or coincident with ce# = low , ; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc (4) t ow write cycle 2 (ce# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc notes : 1.we#, ce# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance stat e. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? data retention characteristics parameter symbol test cond ition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v 2.0 - 5.5 v data retention current i dr v cc = 2.0v ce# v R cc - 0.2v normal - 0.6 3 ma v cc = 2.0v ce# v R cc - 0.2v others at 0.2v or v cc -0.2v ll - 0.5 20 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform vcc ce# v dr R 2.0v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.)
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? package outline dimension 28 pin 300 mil pdip package outline dimension
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? 28-pin 300 mil soj package outline dimension 1 28 14 15 a2 l c xx x note : 1.s/e/d dimension is not including mold flash. 2.the end flash in package lengthwise is not more than 10 mils each side. unit sym. inch(ref) mm(base) a 0.140(m a x) 3.556(m a x) a 1 0.025(min) 0.635(min) a2 0.100 0.015 2.540 0.381 b 0.018 0.004 0.457 0.102 b1 0.028 0.004 0.711 0.102 c 0.010 0.004 0.254 0.102 d 0.710 0.020 18.03 0.508 e 0.337 0.010 8.560 0.254 e1 0.300 0.005 7.620 0.127 e 0.050 0.006 1.270 0.152 l 0.087 0.010 2.210 0.254 s 0.045(max) 1.143(max) y 0.004(max) 0.102(max)
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? 28 pin 8x13.4mm stsop package outline dimension 1 14 15 28 c l hd d "a" b e e 12 (2x) 12 (2x) seating plane y 28 15 14 1 c a2 a1 l a 0.254 0 gauge plane 12 (2x) 12 (2x) seating plane "a" datail view l1 symbols dimensions in millimeters dimensions in inches min nom max min nom max a 1.00 1.10 1.20 0.040 0.043 0.047 a 1 0.05 - 0.15 0.002 - 0.006 a 2 0.91 1.00 1.05 0.036 0.039 0.041 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.07 0.15 0.23 0.003 0.006 0.009 hd 13.20 13.40 13.60 0.520 0.528 0.535 d 11.60 11.80 12.00 0.457 0.465 0.472 e 7.80 8.00 8.20 0.307 0.315 0.323 e - 0.55 - - 0.0216 - l 0.30 0.50 0.70 0.012 0.020 0.028 l1 0.675 - - 0.027 - - y 0.00 - 0.076 0.000 - 0.003 0 3 5 0 3 5
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? ordering information
ly61256 rev. 1.7 32k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 12 ? this page is left blank intentionally.

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